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1 data sheet acquired from harris semiconductor schs155c features buffered inputs asynchronous master reset typical f max = 60mhz at v cc = 5v, c l = 15pf, t a = 25 o c fanout (over temperature range) - standard outputs . . . . . . . . . . . . . . . 10 lsttl loads - bus driver outputs . . . . . . . . . . . . . 15 lsttl loads wide operating temperature range . . . -55 o c to 125 o c balanced propagation delay and transition times signi?ant power reduction compared to lsttl logic ics hc types - 2v to 6v operation - high noise immunity: n il = 30%, n ih = 30% of v cc at v cc = 5v hct types - 4.5v to 5.5v operation - direct lsttl input logic compatibility, v il = 0.8v (max), v ih = 2v (min) - cmos input compatibility, i l 1 a at v ol , v oh description the ?c164 and ?ct164 are 8-bit serial-in parallel-out shift registers with asynchronous reset. data is shifted on the positive edge of clock (cp). a low on the master reset ( mr) pin resets the shift register and all outputs go to the low state regardless of the input conditions. two serial data inputs (ds1 and ds2) are provided, either one can be used as a data enable control. pinout cd54hc164, cd54hct164 (cerdip) cd74hc164, cd74hct164 (pdip, soic) top view ordering information part number temp. range ( o c) package CD54HC164F3A -55 to 125 14 ld cerdip cd54hct164f3a -55 to 125 14 ld cerdip cd74hc164e -55 to 125 14 ld pdip cd74hc164m -55 to 125 14 ld soic cd74hc164mt -55 to 125 14 ld soic cd74hc164m96 -55 to 125 14 ld soic cd74hct164e -55 to 125 14 ld pdip cd74hct164m -55 to 125 14 ld soic cd74hct164mt -55 to 125 14 ld soic cd74hct164m96 -55 to 125 14 ld soic note: when ordering, use the entire part number. the suf? 96 denotes tape and reel. the suf? t denotes a small-quantity reel of 250. ds1 ds2 q 0 q 1 q 2 q 3 gnd v cc q 7 q 6 q 5 q 4 mr cp 1 2 3 4 5 6 7 14 13 12 11 10 9 8 october 1997 - revised august 2003 caution: these devices are sensitive to electrostatic discharge. users should follow proper ic handling procedures. copyright 2003, texas instruments incorporated cd54hc164, cd74hc164, cd54hct164, cd74hct164 high-speed cmos logic 8-bit serial-in/parallel-out shift register [ /title ( cd74 h c164 , c d74 h ct16 4 ) / sub- j ect ( high s peed c mos l ogic 8 -bit s erial- i n/par- a llel-
2 functional diagram truth table operating mode inputs outputs mr cp ds1 ds2 q 0 q 1 - q 7 reset (clear) l x x x l l - l shift h lll q 0 - q 6 h lhl q 0 - q 6 h hll q 0 - q 6 h hhh q 0 - q 6 h= high voltage level. h= high voltage level one set-up time prior to the low-to-high clock transition. l= low voltage level one set-up time prior to the low-to-high clock transition. l= low voltage level. x= don? care. = transition from low to high level. q n = lower case letters indicate the state of the reference input clock transition. 3 4 5 6 11 13 12 10 1 ds1 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 cp mr 98 2 ds2 gnd = 7 v cc = 14 cd54hc164, cd74hc164, cd54hct164, cd74hct164
3 absolute maximum ratings thermal information dc supply voltage, v cc . . . . . . . . . . . . . . . . . . . . . . . . -0.5v to 7v dc input diode current, i ik for v i < -0.5v or v i > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . . . 20ma dc output diode current, i ok for v o < -0.5v or v o > v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 20ma dc output source or sink current per output pin, i o for v o > -0.5v or v o < v cc + 0.5v . . . . . . . . . . . . . . . . . . . . 25ma dc v cc or ground current, i cc or i gnd . . . . . . . . . . . . . . . . . . 50ma operating conditions temperature range (t a ) . . . . . . . . . . . . . . . . . . . . . -55 o c to 125 o c supply voltage range, v cc hc types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2v to 6v hct types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5v to 5.5v dc input or output voltage, v i , v o . . . . . . . . . . . . . . . . . 0v to v cc input rise and fall time 2v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (max) 4.5v. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (max) 6v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (max) thermal resistance (typical, note 1) ja ( o c/w) e (pdip) package . . . . . . . . . . . . . . . . . . . . . . . . . . 80 m (soic) package. . . . . . . . . . . . . . . . . . . . . . . . . . 86 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . 150 o c maximum storage temperature range . . . . . . . . . .-65 o c to 150 o c maximum lead temperature (soldering 10s) . . . . . . . . . . . . . 300 o c (soic - lead tips only) caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress only rating and operatio n of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not im plied. note: 1. the package thermal impedance is calculated in accordance with jesd 51-7. dc electrical speci?ations parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hc types high level input voltage v ih - - 2 1.5 - - 1.5 - 1.5 - v 4.5 3.15 - - 3.15 - 3.15 - v 6 4.2 - - 4.2 - 4.2 - v low level input voltage v il - - 2 - - 0.5 - 0.5 - 0.5 v 4.5 - - 1.35 - 1.35 - 1.35 v 6 - - 1.8 - 1.8 - 1.8 v high level output voltage cmos loads v oh v ih or v il -0.02 2 1.9 - - 1.9 - 1.9 - v -0.02 4.5 4.4 - - 4.4 - 4.4 - v -0.02 6 5.9 - - 5.9 - 5.9 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v -5.2 6 5.48 - - 5.34 - 5.2 - v low level output voltage cmos loads v ol v ih or v il 0.02 2 - - 0.1 - 0.1 - 0.1 v 0.02 4.5 - - 0.1 - 0.1 - 0.1 v 0.02 6 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v 5.2 6 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc or gnd -6-- 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 6 - - 8 - 80 - 160 a cd54hc164, cd74hc164, cd54hct164, cd74hct164
4 hct types high level input voltage v ih - - 4.5 to 5.5 2- - 2 - 2 - v low level input voltage v il - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 v high level output voltage cmos loads v oh v ih or v il -0.02 4.5 4.4 - - 4.4 - 4.4 - v high level output voltage ttl loads -4 4.5 3.98 - - 3.84 - 3.7 - v low level output voltage cmos loads v ol v ih or v il 0.02 4.5 - - 0.1 - 0.1 - 0.1 v low level output voltage ttl loads 4 4.5 - - 0.26 - 0.33 - 0.4 v input leakage current i i v cc to gnd 0 5.5 - - 0.1 - 1- 1 a quiescent device current i cc v cc or gnd 0 5.5 - - 8 - 80 - 160 a additional quiescent device current per input pin: 1 unit load ? i cc (note 2) v cc -2.1 - 4.5 to 5.5 - 100 360 - 450 - 490 a note: 2. for dual-supply systems theoretical worst case (v i = 2.4v, v cc = 5.5v) specification is 1.8ma. dc electrical speci?ations (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units v i (v) i o (ma) min typ max min max min max hct input loading table input unit loads date shift-in (1, 2) 0.3 mr 0.9 clock 0.7 note: unit load is ? i cc limit speci?d in dc electrical speci?ations table, e.g. 360 a max at 25 o c. prerequisite for switching function parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max hc types maximum clock frequency f max 2 6-5-4-mhz 4.5 30 - 24 - 20 - mhz 6 35 - 28 - 24 - mhz mr pulse width t w 2 60-75-90-ns 4.5 12 - 15 - 18 - ns 6 10-13-15-ns cd54hc164, cd74hc164, cd54hct164, cd74hct164
5 cp pulse width t w 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14-17-20-ns set-up time t su 2 60-75-90-ns 4.5 12 - 15 - 18 - ns 6 10-13-15-ns hold time t h 2 4-4-4-ns 4.54-4-4-ns 6 4-4-4-ns mr to clock, removal time t rem 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14-17-20-ns hct types maximum clock frequency f max 4.5 27 - 22 - 18 - mhz mr pulse width t w 6 18-23-27-ns cp pulse width t w 4.5 18 - 23 - 27 - ns set-up time t su 6 12-15-18-ns hold time t h 4.54-4-4-ns mr to clock, removal time t rem 6 16-20-24-ns switching speci?ations input t r , t f = 6ns parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max hc types propagation delay, cp to q n t plh , t phl c l = 50pf 2 - 170 212 255 ns 4.5 - 34 43 51 ns c l = 15pf 5 14 - - - ns c l = 50pf 6 - 29 36 43 ns mr to q n t plh , t phl c l = 50pf 2 - 140 175 210 ns 4.5 - 28 35 42 ns c l = 15pf 5 11 - - - ns c l = 50pf 6 - 24 30 36 ns output transition times t tlh , t thl c l = 50pf 2 - 75 - 110 ns 4.5 - 15 - 22 ns 6 - 13 - 19 ns maximum clock frequency f max c l = 15pf 5 60 - - - mhz input capacitance c in ---1010 10pf prerequisite for switching function (continued) parameter symbol v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units min max min max min max cd54hc164, cd74hc164, cd54hct164, cd74hct164
6 power dissipation capacitance (notes 3, 4) c pd - 5 47 - - - pf hct types propagation delay, cp to q n t plh , t phl c l = 50pf 4.5 - 36 45 54 ns c l = 15pf 5 15 - - - ns mr to q n t plh , t phl c l = 50pf 4.5 - 38 46 57 ns c l = 15pf 5 16 - - - ns output transition times t tlh , t thl c l = 50pf 4.5 - 15 19 22 ns input capacitance c in ---- - -pf maximum clock frequency f max c l = 15pf - 54 - - - mhz power dissipation capacitance (notes 3, 4) c pd - 5 49 10 10 10 pf notes: 3. c pd is used to determine the dynamic power consumption, per device. 4. p d =v cc 2 f i + (c l v cc 2 +f o ) where f i = input frequency, f o = output frequency, c l = output load capacitance, v cc = supply voltage. switching speci?ations input t r , t f = 6ns (continued) parameter symbol test conditions v cc (v) 25 o c -40 o c to 85 o c -55 o c to 125 o c units typ max max max test circuits and waveforms figure 1. hc setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits figure 2. hct setup times, hold times, removal time, and propagation delay times for edge triggered sequential logic circuits t r c l t f c l gnd v cc gnd v cc 50% 90% 10% gnd clock input data input output set, reset or preset v cc 50% 50% 90% 10% 50% 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) t h(h) t r c l t f c l gnd 3v gnd 3v 1.3v 2.7v 0.3v gnd clock input data input output set, reset or preset 3v 1.3v 1.3v 1.3v 90% 10% 1.3v 90% t rem t plh t su(h) t tlh t thl t h(l) t phl ic c l 50pf t su(l) 1.3v t h(h) 1.3v cd54hc164, cd74hc164, cd54hct164, cd74hct164
packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) 5962-8970401ca active cdip j 14 1 tbd a42 snpb n / a for pkg type cd54hc164f active cdip j 14 1 tbd a42 snpb n / a for pkg type CD54HC164F3A active cdip j 14 1 tbd a42 snpb n / a for pkg type cd54hct164f3a active cdip j 14 1 tbd a42 snpb n / a for pkg type cd74hc164e active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc164ee4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hc164m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164m96g4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164mg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hc164mtg4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164e active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hct164ee4 active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type cd74hct164m active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164m96 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164m96e4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164m96g4 active soic d 14 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164me4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164mg4 active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164mt active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164mte4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim cd74hct164mtg4 active soic d 14 250 green (rohs & no sb/br) cu nipdau level-1-260c-unlim package option addendum www.ti.com 9-oct-2007 addendum-page 1
(1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 9-oct-2007 addendum-page 2
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant cd74hc164m96 soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 cd74hct164m96 soic d 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 q1 package materials information www.ti.com 11-mar-2008 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) cd74hc164m96 soic d 14 2500 346.0 346.0 33.0 cd74hct164m96 soic d 14 2500 346.0 346.0 33.0 package materials information www.ti.com 11-mar-2008 pack materials-page 2

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